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HD64F2149YV bảng dữ liệu(PDF) 174 Page - Renesas Technology Corp |
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HD64F2149YV bảng dữ liệu(HTML) 174 Page - Renesas Technology Corp |
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174 / 1075 page  Section 6 Bus Controller Rev. 3.00 Jan 18, 2006 page 146 of 1044 REJ09B0280-0300 Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) Bus Specifications (Basic Bus Interface) ABW AST WMS1 WMS0 WC1 WC0 Bus Width Access States Program Wait States 00 ——— — 16 2 0 10 1 —— 16 3 0 —* —* 00 3 0 11 10 2 13 10 ——— — 82 0 10 1 —— 83 0 —* —* 00 3 0 11 10 2 13 Note: * Except when WMS1 = 0 and WMS0 = 1 6.3.2 Advanced Mode The initial state of the external space is basic bus interface, three-state access space. In ROM- enabled expanded mode, the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. 6.3.3 Normal Mode The initial state of the external memory space is basic bus interface, three-state access space. In ROM-disabled expanded mode, the space excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled expanded mode, the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on- chip RAM is disabled and the corresponding space becomes external space. |
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