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HD64F2149YV bảng dữ liệu(PDF) 167 Page - Renesas Technology Corp |
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HD64F2149YV bảng dữ liệu(HTML) 167 Page - Renesas Technology Corp |
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167 / 1075 page ![]() Section 6 Bus Controller Rev. 3.00 Jan 18, 2006 page 139 of 1044 REJ09B0280-0300 Section 6 Bus Controller 6.1 Overview The H8S/2169 or H8S/2149 has a built-in bus controller (BSC) that allows external address space bus specifications, such as bus width and number of access states, to be set. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below. • Basic bus interface 2-state access or 3-state access can be selected Program wait states can be inserted • Burst ROM interface External space can be designated as ROM interface space 1-state or 2-state burst access can be selected • Idle cycle insertion An idle cycle can be inserted when an external write cycle immediately follows an external read cycle • Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC |
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