HD64F2149YV datasheet(162/1075 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 3.00 Jan 18, 2006 page 134 of 1044

REJ09B0280-0300

5.6

Usage Notes

5.6.1

Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective

after execution of the instruction.

In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or

MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will

still be enabled on completion of the instruction, and so interrupt exception handling for that

interrupt will be executed on completion of the instruction. However, if there is an interrupt

request of higher priority than that interrupt, interrupt exception handling will be executed for the

higher-priority interrupt, and the lower-priority interrupt will be ignored.

The same also applies when an interrupt source flag is cleared to 0.

Figure 5.12 shows an example in which the CMIEA bit in 8-bit timer register TCR is cleared to 0.

Internal

address bus

Internal

write signal

CMIEA

CMFA

CMIA

interrupt signal

TCR write cycle by CPU

CMIA exception handling

TCR address

Figure 5.12 Contention between Interrupt Generation and Disabling

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while

the interrupt is masked.

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