HD64F2149YV datasheet(105/1075 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 77 of 1044

REJ09B0280-0300

2.9.5

External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or

three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to

section 6, Bus Controller.

2.10

Usage Note

2.10.1

TAS Instruction

Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS

instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers.

If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0,

ER1, ER4, or ER5 is used.

2.10.2

STM/LDM Instruction

ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM

instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored

by one STM/LDM instruction. The following ranges can be specified in the register list.

Two registers: ER0—ER1, ER2—ER3, or ER4—ER5

Three registers: ER0—ER2 or ER4—ER6

Four registers: ER0—ER3

The STM/LDM instruction including ER7 is not generated by the Renesas Technology H8S and

H8/300 series C/C++compilers.

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