HD64F2149YV datasheet(464/1075 Pages) RENESAS

464 / 1075 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 3.00 Jan 18, 2006 page 436 of 1044

REJ09B0280-0300

Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.

Bit 5

Description

Transmission disabled*

(Initial value)

Transmission enabled*

Notes: 1. The TDRE flag in SSR is fixed at 1.

2. In this state, serial transmission is started when transmit data is written to TDR and the

TDRE flag in SSR is cleared to 0.

SMR setting must be performed to decide the transmission format before setting the TE

bit to 1.

Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.

Bit 4

Description

Reception disabled*

(Initial value)

Reception enabled*

Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which

retain their states.

2. Serial reception is started in this state when a start bit is detected in asynchronous

mode or serial clock input is detected in synchronous mode.

SMR setting must be performed to decide the reception format before setting the RE bit

to 1.

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR

set to 1.

The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.

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