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Giải thích chi tiết về linh kiện  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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Section 14 Watchdog Timer (WDT)
Rev. 3.00 Jan 18, 2006 page 421 of 1044
REJ09B0280-0300
14.3.4
RESO
RESO
RESO
RESO Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/
NMI
bit is 1 at this time, an internal reset signal is generated for the entire chip, and at the same time a
low-level signal is output from the
RESO pin. The timing is shown in figure 14.6.
φ
TCNT
H'FF
H'00
132 states
518 states
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
Figure 14.6
RESO
RESO
RESO
RESO Signal Output Timing
14.4
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in
watchdog timer mode, an overflow generates an NMI interrupt request.



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