M32CSLASH8B datasheet(386/406 Pages) RENESAS

386 / 406 page

Under development

M32C/8B Group

25. Usage Notes

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 369 of 385

25.7

Interrupts

25.7.1

ISP Setting

After reset, ISP is initialized to 000000h. The program may go out of control if an interrupt is acknowledged

before setting a value to ISP. Therefore, ISP must be set before any interrupt request is acknowledged. Setting

ISP to an even address allows interrupt sequences to be executed at a higher speed.

To use the NMI interrupt, set ISP at the very beginning of the program. The NMI interrupt can be

acknowledged after the first instruction has been executed after reset.

25.7.2

NMI Interrupt

• The NMI interrupt cannot be disabled. Connect the NMI pin to VCC1 via a resistor (pull-up) when not in

use.

• The P8_5 bit in the P8 register indicates the voltage level applied to the NMI pin. Read the P8_5 bit only to

determine the pin level after the NMI interrupt occurs.

25.7.3

INT Interrupt

• Edge Sensitive

Each “H” or “L” width of the signal applied to pins INT0 to INT5 must be 250 ns or more regardless of

the CPU clock frequency.

• Level Sensitive

Each “H” or “L” width of the signal applied to pins INT0 to INT5 must be one CPU clock cycle + 200 ns

or more. For example, each “H” or “L” width must be 234 ns or more if the CPU clock is 30 MHz.

• The IR bit in the INTiIC register (i = 0 to 5) may become 1 (interrupt requested) when the polarity settings

of pins INT0 to INT5 are changed. Set the IR bit to 0 (interrupt not requested) after the polarity setting is

changed.

Figure 25.3 shows a procedure to set the INTi interrupt source (i = 0 to 5).

M32C/8B bảng dữ liệu(PDF) 386 Page - Renesas Technology Corp