M32CSLASH8B datasheet(382/406 Pages) RENESAS

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M32C/8B Group

25. Usage Notes

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 365 of 385

25.5

Clock Generation Circuits

25.5.1

Main Clock

• If the main clock is selected as the CPU clock while an external clock is applied to the XIN pin, do not stop

the external clock.

(Technical update: TN-M16C-109-0309)

• When a clock applied to the XIN pin is used for the CPU clock, do not set the CM05 bit in the CM0 register

to 1 (stopped).

25.5.2

Sub Clock

25.5.2.1

To Oscillate Sub Clock

To oscillate the sub clock, set the CM07 bit in the CM0 register to 0 (clock other than the sub clock) and the

CM03 bit to 1 (XCIN-XOUT drive capability = high). Then, set the CM04 bit in the CM0 register to 1 (XCIN-

XCOUT oscillation function). Once the sub clock becomes stabilized, set the CM03 bit to 0 (XCIN-XOUT

drive capability = low).

After the above procedure, the sub clock can be used as the CPU clock, or the count source for timer A and

timer B.

(Technical update: TN-16C-119A/EA)

25.5.2.2

Oscillation Parameter Matching

If an oscillation circuit constant matching for the sub clock oscillation circuit has only been evaluated with the

drive capability = high, the constant matching for drive capability = low must also be evaluated.

Contact your oscillator manufacturer for details on the oscillation circuit constant matching.

25.5.3

Clock Dividing Ratio

To change bits MCD4 to MCD0, set the PM12 bit in the PM1 register to 0 (no wait state).

25.5.4

Power Consumption Control

Stabilize the main clock, sub clock, or PLL clock prior to switching the clock source for the CPU clock to one

of these clocks.

25.5.4.1

Wait Mode

• When entering wait mode, the instructions following the WAIT instruction are stored into the instruction

queue, and the program stops. Insert at least 4 NOP instructions after the WAIT instruction.

• To enter wait mode, execute the WAIT instruction while a high-level (“H”) signal is applied to the NMI

pin.

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