M32CSLASH8B datasheet(390/406 Pages) RENESAS

390 / 406 page

Under development

M32C/8B Group

25. Usage Notes

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 373 of 385

25.9

Timers

25.9.1

Timer A, Timer B

Timers are stopped after reset. Set the TAiS (i = 0 to 4) or TBjS (j = 0 to 5) bit in the TABSR or TBSR register

to 1 (count starts) after setting timer operating mode, count source, and counter value.

Change the following registers and bits while the corresponding timer is stopped (the TAiS or TBjS bit is set to

0 (count stops)).

• Registers TAiMR and TBjMR

• UDF register

• Bits TAZIE, TA0TGL, and TA0TGH in the ONSF register

• TRGSR register

25.9.2

Timer A

25.9.2.1

Timer A (Timer Mode)

• The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1

(count starts) after selecting timer operating mode and setting the TAi register.

• The TAi register indicates a counter value while counting at any given time. However, FFFFh can be read

in the reload timing. When the TAi register is set while a counter is stopped, the setting value can be read

until a counter is started.

25.9.2.2

Timer A (Event Counter Mode)

• The TAiS bit (i = 0 to 4) is set to 0 (count stops) after reset. Set the TAiS bit to 1 (count starts) after

selecting timer operating mode and setting the TAi register.

• The TAi register indicates a counter value while counting at any given time. In the reload timing, however,

FFFFh can be read if the timer underflows, or 0000h if the timer overflows. When the TAi register is set

while the counter is stopped, the setting value can be read until a counter is started.

M32C/8B bảng dữ liệu(PDF) 390 Page - Renesas Technology Corp