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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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M16C/29 bảng dữ liệu(PDF) 177 Page - Renesas Technology Corp |
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M16C/29 bảng dữ liệu(HTML) 177 Page - Renesas Technology Corp |
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177 / 499 page  13. Timer S p u o r G 9 2 / C 6 1 M page 153 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 13.12 Counter Increment Mode Figure 13.13 Counter Increment/Decrement Mode FFFF16 800016 000016 400016 C00016 State of a counter Base Timer interrupts 1 0 b14 overflow signal 1 0 b15 overflow signal Base Timer interrupt IT=0 in the G1BCR0 register (Base timer interrupt generated by the bit 15 overflow) IT=1 in the G1BCR0 register (Base timer interrupt generated by the bit 14 overflow) The above applies to the following conditions. The RST4 bit in the G1BCR0 register is set to 0 (the base timer is not reset by matching the G1BTRR register) The RST1 bit in the G1BCR1 register is set to 0 (the base timer is not reset by matching the G1PO0 register) Bits UD1 to UD0 in the G1BCR1 register are set to 002 (counter increment mode) FFFF16 800016 400016 C00016 000016 State of a counter 1 0 Base Timer interrupts b14 overflow signal 1 0 b15 overflow signal Base Timer interrupt IT=0 in the G1BCR0 register (Base timer interrupt generated by the bit 15 overflow) IT=1 in the G1BCR0 register (Base timer interrupt generated by the bit 14 overflow) |
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