M16CSLASH29 datasheet(176/499 Pages) RENESAS

176 / 499 page

13. Timer S

page 152

Table 13.3 Base Timer Associated Register Settings (Time Measurement Function, Waveform

Generation Function, Communication Function)

Bit

Function

G1BCR0

BCK1 to BCK0

Select a count source

RST4

Select base timer reset timing

Select the base timer overflow

G1BCR1

RST2 to RST1

Select base timer reset timing

BTS

Used to start the base timer

UD1 to UD0

Select how to count

G1BT

Read or write base timer value

G1DV

Divide ratio of a count source

Set the following registers to set the RST1 bit to 1 (base timer reset by matching the base timer with the G1PO0 register)

G1POCR0

MOD1 to MOD0

Set to 002 (single-phase waveform output mode)

G1PO0

Set reset cycle

G1FS

FSC0

Set to 0 (waveform generating function)

G1FE

IFE0

Set to 1 (channel operation start)

Figure 13.11 Base Timer Block Diagram

(n+1) divider

RST4

RST1

RST2

Matched with G1BTRR

Matched with G1PO0 register

Base timer

b14 b15

Base timer

overflow request

BCK1 to BCK0

BTS bit in G1BCR1 register

Two-phase pulse input

Overflow signal

Input "L" to INT1 pin

Base timer reset

fBT1

NOTE:

1. Divider is reset when the BTS bit is set to 0.

IT, RST4, BCK1 to BCK0: Bits in the G1BCR0 register

RST2 to RST1: Bits in the G1BCR1 register

(Note 1)

f1 or f2

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