M16CSLASH29 datasheet(135/499 Pages) RENESAS

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12. Timer A

page 111

12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing

This function initializes the timer count value to 0 by Z-phase (counter initialization) input during two-

phase pulse signal processing.

This function can only be used in timer A3 event counter mode during two-phase pulse signal process-

_______

ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.

Counter initialization by Z-phase input is enabled by writing 000016 to the TA3 register and setting the

TAZIE bit in ONSF register to 1 (Z-phase input enabled).

Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-

sen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse

_______

width applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count

source.

The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.10 shows

the relationship between the two-phase pulse (A phase and B phase) and the Z phase.

If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3

interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this

function.

Figure 12.10 Two-phase Pulse (A phase and B phase) and the Z Phase

m+1

TA3OUT

(A phase)

Count source

TA3IN

(B phase)

Timer A3

INT2

(Z phase)

(1)

Input equal to or greater than one clock cycle

of count source

NOTE:

1. This timing diagram is for the case where the POL bit in the INT2IC register is set to 1 (rising edge).

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