M16CSLASH29 datasheet(134/499 Pages) RENESAS

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12. Timer A

page 110

Figure 12.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse

signal processing with timer A2, A3 or A4)

Timer Ai Mode Register (i=2 to 4)

(When using two-phase pulse signal processing)

Symbol

Address

After Reset

TA2MR to TA4MR

039816 to 039A16

0016

b6 b5 b4 b3 b2 b1 b0

Operation mode select bit

0 1: Event counter mode

b1 b0

TMOD1

TMOD0

MR0

To use two-phase pulse signal processing, set this bit to 0

MR2

MR1

MR3

TCK1

TCK0

Bit Name

Function

Count operation type

select bit

Two-phase pulse signal

processing operation

select bit (1)(2)

0: Reload type

1: Free-run type

0: Normal processing operation

1: Multiply-by-4 processing operation

To use two-phase pulse signal processing, set this bit to 0

To use two-phase pulse signal processing, set this bit to 1

To use two-phase pulse signal processing, set this bit to 0

Bit Symbol

NOTES:

1. The TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate

in normal processing mode and x4 processing mode, respectively.

2. If two-phase pulse signal processing is desired, following register settings are required:

• Set the TAiP bit in the UDF register to 1 (two-phase pulse signal processing function enabled).

• Set bits TAiTGH and TAiTGL in the TRGSR register to 002 (TAiIN pin input).

• Set the port direction bits for TAiIN and TAiOUT to 0 (input mode).

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