M32C83T datasheet(124/527 Pages) RENESAS

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10. Interrupts

)

(

Table 10.4 Interrupt Sequence Execution Time

8-Bit Bus

16 cycles

14 cycles

15 cycles

16 cycles

19 cycles

21 cycles

16-Bit Bus

14 cycles

16 cycles

12 cycles

14 cycles

13 cycles

14 cycles

17 cycles

19 cycles

Interrupt Vector Address

Even address

Odd address(1)

Even address

Odd address(1)

Even address(2)

Even address

Odd address(1)

Even address(2)

Vector table is internal register

Interrupt

Peripheral Function

INT Instruction

_______

NMI

Watchdog Timer

Undefined Instruction

Address Match

Overflow

BRK Instruction (relocatable vector table)

BRK Instruction (fixed vector table)

High-Speed Interrupt

5 cycles

NOTES:

1. Allocate interrupt vectors to even addresses.

2. Vectors are fixed to even addresses.

10.6.5 IPL Change when Interrupt Request is Acknowledged

When a peripheral function interrupt request is acknowledged, IPL sets the priority level for the acknowl-

edged interrupt.

Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has

no interrupt priority level is acknowledged, the value shown in Table 10.5 is set in IPL as the interrupt

priority level.

Table 10.5 Interrupts without Interrupt Priority Levels and IPL

Interrupt Sources

Level that is Set to IPL

_______

Watchdog Timer, NMI, Oscillation Stop Detect

Reset

Software, Address Match

Not changed

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