M32C83T datasheet(125/527 Pages) RENESAS

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Page 102

10. Interrupts

)

(

10.6.6 Saving a Register

In the interrupt sequence, the FLG register and PC are saved to the stack.

After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32

bits, are saved to the stack. Figure 10.7 shows the stack state before and after an interrupt request is

acknowledged.

Other important registers are saved by program at the beginning of an interrupt service routine. The

PUSHM instruction can save all registers except SP.

Refer to 10.4 High-Speed Interrupt for the high-speed interrupt.

[SP]

SP value before

interrupt is

generated

Stack state before an interrupt request is acknowledged

Address

Stack state after an interrupt request is acknowledged

m-6

m-5

m–4

m–3

m–2

m–1

m+1

LSB

MSB

LSB

MSB

Address

The Stack

FLGL

PCH

FLGH

Content of

previous stack

Content of

previous stack

Content of

previous stack

Content of

previous stack

PCL

PCM

[SP]

New SP value

m-6

m-5

m–4

m–3

m–2

m–1

m+1

0016

Figure 10.7 Stack States

10.6.7 Restoration from Interrupt Routine

When the REIT instruction is executed at the end of an interrupt service routine, the FLG register and PC,

which have been saved to the stack, are automatically restored. The program, executed before an interrupt

request has been acknowledged, starts running again. Refer to 10.4 High-Speed Interrupt for the high-

speed interrupt.

Restore registers saved by program in an interrupt service routine by the POPM instruction or others

before the REIT and FREIT instructions. Register bank is switched back to the bank used prior to the

interrupt sequence by the REIT or FREIT instruction.

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