M32C83T datasheet(78/527 Pages) RENESAS

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7. Bus

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7.2 Bus Control

Signals required to access external devices are provided and software wait states are inserted as follows.

The signals are available in memory expansion mode and microprocessor mode only.

7.2.1 Address Bus and Data Bus

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The address bus is a signal accessing 16M-byte space and uses 24 control pins; A0 to A22 and A23. A23

is the inversed output signal of the highest-order address bit.

The data bus is a signal which inputs and outputs data. The DS register selects the 8-bit data bus from D0

to D7 or the 16-bit data bus from D0 to D15 for each external space. When applying an "H" signal to the

BYTE pin, the data bus accessing the external memory space 3 becomes the 8-bit data bus after reset.

When applying an "L" signal to the BYTE pin, the data bus accessing the external memory space 3

becomes the 16-bit data bus.

When changing single-chip mode to memory expansion mode, the address bus is in an indeterminate

state until the microcomputer accesses an external memory space.

When using the DRAMC to access DRAM area, row addresses and column addresses are multiplexed

and output via A8 to A20.

7.2.2 Chip-Select Signal

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The chip-select signal shares ports with A0 to A22 and A23. The PM11 to PM10 bits in the PM1 register

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determine which CS area is accessed and how many chip-select signals are output. A maximum of four

chip-select signals can be output.

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In microprocessor mode, the chip-select signal is not output after reset. A23, however, can perform as the

chip-signal signal.

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The chip-select signal becomes "L" while the microcomputer accesses the external CSi area (i=0 to 3). It

becomes high ("H") when the microcomputer accesses another external memory space or an internal

memory space. Figure 7.2 shows an example of the address bus and chip-select signal output.

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