M32C83T datasheet(77/527 Pages) RENESAS

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Page 54

7. Bus

)

(

Table 7.2 Processor Mode and Port Function

Access all CS Areas using

the Separate Bus

Single-

Chip Mode

Memory Expansion Mode/ Microprocessor Mode

Memory Expansion Mode

Data Bus Width

"012", "102""002"

"112"(1)

Access all

external space with

8-bit data bus

NOTES:

1. The PM05 to PM04 bits cannot be set to "112" (access all CS areas using multiplexed bus) in

microprocessor mode because the microcomputer starts operation using the separate bus after reset.

When the PM05 to PM04 bits are set to "112" in memory expansion mode, the microcomputer accesses

64K-byte memory space per chip select using the address bus .

2. These ports become address buses when accessing space using the separate bus.

3. The PM15 to PM14 bits in the PM1 register determine which pin outputs the ALE signal. The PM02 bit in

the PM0 register selects either "WRL,WRH" or "BHE,WR" combination. P56 provides an indeterminate

output when the PM15 and PM14 bits to "002" (no ALE). It cannot be used as an I/O port.

4. When DRAMC is selected to access DRAM area, CASL, CASH, DW, BCLK become output pins.

5. The PM11 to PM10 bits in the PM1 register determine the CS signal and address bus.

PM05 to

PM04 Bits in

PM0 Register

CS (Chip-select signal) or Address bus (A23)

(Refer to 7.2 Bus Control for details)(4)

Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK

(Refer to 7.2 Bus Control for details)(3)

P00 to P07

P10 to P17

Data bus

D0 to D7

I/O port

P20 to P27

I/O port

P30 to P37

I/O port

Address bus/

Data bus(2)

A8/D8 to A15/D15

P40 to P43

I/O port

P44 to P46

I/O port

P47

I/O port

P50 to P53

I/O port

P54

I/O port

P55

I/O port

P56

I/O port

P57

I/O port

HOLD

RAS (3)

RDY

Access CS1 or CS2 using

the Multiplexed Bus

Access All Other CS Areas using

the Separate Bus

Data bus

D0 to D7

Data bus

D0 to D7

Data bus

D0 to D7

Address bus/

Data bus(2)

A0/D0 to A7/D7

Address bus

A0 to A7

Address bus

A0 to A7

Address bus/

Data bus

A0/D0 to A7/D7

Address bus/

Data bus

A0/D0 to A7/D7

Address bus

A8 to A15

Address bus

A8 to A15

Address bus

A8 to A15

Address bus

A8 to A15

Address bus

A16 to A19

Address bus

A16 to A19

Address bus

A16 to A19

Address bus

A16 to A19

Data bus

D8 to D15

Data bus

D8 to D15

Address bus/

Data bus

A8/D8 to A15/D15

Access all CS Areas using

the Multiplexed Bus

Access one or more

external space with

16-bit data bus

Access all

external space with

8-bit data bus

Access one or more

external space with

16-bit data bus

Access all

external space with

8-bit data bus

Access one or more

external space with

16-bit data bus

CS (Chip-select signal) or Address bus (A20 to A22)

(Refer to 7.2 Bus Control for details)(4)

HLDA (3)

RAS (3)

Processor

Mode

Address bus/

Data bus(2)

A0/D0 to A7/D7

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