M32C83T datasheet(87/527 Pages) RENESAS

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Page 64

7. Bus

)

(

Table 7.7 Microcomputer Status in a Hold State

Item

Status

Oscillation

_____

_______

RD Signal, WR Signal, Address Bus, Data Bus, BHE,

High-impedance

_______

CS0 to CS3

Programmable I/O Ports: P0 to P15

__________

Maintains the same state as when HOLD signal

is received

__________

HLDA

Output "L"

Internal Peripheral Circuits

On (excluding the watchdog timer)

ALE Signal

Output "L"

7.2.8 External Bus State when Accessing Internal Space

Table 7.8 shows external bus states when an internal space is accessed.

Table 7.8 External Bus State when Accessing Internal Space

Item

State when accessing SFR, internal ROM and internal RAM

Address bus

Holds an address of an external space accessed just before

Data Bus

When Read

High-impedance

When Write

High-impedance

_____

______

________

_________

RD, WR, WRL, WRH

Output "H"

________

BHE

Holds state of external space last accessed

_______

CS0 to CS3

Output "H"

ALE

Output ALE

7.2.9 BCLK Output

The CPU clock operates the CPU. When combining the PM07 bit in the PM0 register set to "0" (BCLK

output) and the CM01 to CM00 bits in the CM0 register set to "002", the CPU clock signal is output from

P53 as BCLK.

No BCLK is output in single-chip mode. Refer to 8. Clock Generating Circuit for details.

_______

__________

_____

7.2.10 DRAM Control Signals (RAS, CASL, CASH and DW)

The DRAM control signals control the DRAM. The DRAM control signals are output when the DRAM

area, determined by the AR0 to AR2 bits in the DRAMCONT register, is output. Table 7.9 lists each

signal operation.

_______

__________

_____

Table 7.9 RAS, CASL, CASH and DW Signals

Data Bus State

RAS

CASH

CASL

LLL

Read data from both even and odd addresses

Read 1-byte data from even address

Read 1-byte data from odd address

Write data to both even and odd addresses

Data Bus Width

LHL

8 bits

Write 1-byte data to even address

Write 1-byte data to odd address

Read 1-byte data

Write 1-byte data

16 bits

Not used

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