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HD404848FS bảng dữ liệu(PDF) 78 Page - Renesas Technology Corp |
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HD404848FS bảng dữ liệu(HTML) 78 Page - Renesas Technology Corp |
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78 / 127 page ![]() HD404849 Series 76 • Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit (TRDL) and upper digit (TRDU). See figures 63 and 64. The operation of timer read register D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. Bit Initial value Read/Write Bit name 3 Undefined R TRDL3 2 Undefined R TRDL2 0 Undefined R TRDL0 1 Undefined R TRDL1 Timer read register D (lower digit) (TRDL: $011) Figure 63 Timer Read Register D Lower Digit (TRDL) Bit Initial value Read/Write Bit name 3 Undefined R TRDU3 2 Undefined R TRDU2 0 Undefined R TRDU0 Timer read register D (upper digit) (TRDU: $012) 1 Undefined R TRDU1 Figure 64 Timer Read Register D Upper Digit (TRDU) • Port mode register C (PMRC: $025): Write-only register that selects R2 0/EVND pin function as shown in figure 50. It is reset to $0 by MCU reset. • Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 65. It is reset to $0 by MCU reset. |
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