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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HD404848FS bảng dữ liệu(PDF) 63 Page - Renesas Technology Corp |
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HD404848FS bảng dữ liệu(HTML) 63 Page - Renesas Technology Corp |
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63 / 127 page  HD404849 Series 61 T × (N + 1) T × 256 T T × (256 – N) TMC13 = 0 The waveform is always fixed low when N = $FF. T: N: TMC13 = 1 Input clock period to counter (the clock source and frequency division ratio are controlled in timer mode registers B1, C1, and D1) The value in timer write registers C and D Note: TMD13 = 0 (free-running timer setting) 256 clock cycles 256 clock cycles Free-running timer (1) Toggle output waveform (timers B, C, and D) (2) PWM output waveform (timers C and D) (256 – N) clock cycles (256 – N) clock cycles Reload timer TMD13 = 1 (reload timer setting) Figure 43 Timer Output Waveform Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register C (PMRC: $025) • Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and prescaler division ratio as shown in figure 44. It is reset to $0 by MCU reset. |
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