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HD404324FS bảng dữ liệu(PDF) 23 Page - Renesas Technology Corp |
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HD404324FS bảng dữ liệu(HTML) 23 Page - Renesas Technology Corp |
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23 / 103 page ![]() HD404054 Series/HD404094 Series 21 Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3) IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 9. Table 9 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request 0No 1 Yes Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 10. Table 10 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request 0 Enabled 1 Disabled (masked) Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used, as listed in table 11. Table 11 Timer D Interrupt Request Flag (IFTD: $003, Bit 0) IFTD Interrupt Request 0No 1 Yes |
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