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PSD835G2-70UI bảng dữ liệu(PDF) 60 Page - STMicroelectronics |
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PSD835G2-70UI bảng dữ liệu(HTML) 60 Page - STMicroelectronics |
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60 / 110 page  PSD835G2 PSD8XX Family 59 The PSD835G2 Functional Blocks (cont.) Drive Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Port A Open Open Open Open Open Open Open Open Drain Drain Drain Drain Drain Drain Drain Drain Port B Open Open Open Open Open Open Open Open Drain Drain Drain Drain Drain Drain Drain Drain Port C Slew Slew Slew Slew Slew Slew Slew Slew Rate Rate Rate Rate Rate Rate Rate Rate Port D Open Open Open Open Drain Drain Drain Drain Port E Open Open Open Open Open Open Open Open Drain Drain Drain Drain Drain Drain Drain Drain Port F Slew Slew Slew Slew Slew Slew Slew Slew Rate Rate Rate Rate Rate Rate Rate Rate Port G Open Open Open Open Open Open Open Open Drain Drain Drain Drain Drain Drain Drain Drain Table 23. Drive Register Pin Assignment 9.4.3.3 Drive Select Register The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a ‘1’. The default pin drive is CMOS. Aside: the slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Register is set to ‘1’. The default rate is slow slew. Table 23 shows the Drive Register for Ports A, B, C, D, E, F and G. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for. |
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