PSD835G2-70UI datasheet(64/110 Pages) STMICROELECTRONICS

tên linh kiện	PSD835G2-70UI

Giải thích chi tiết về linh kiện	Configurable Memory System on a Chip for 8-Bit Microcontrollers

PDF	110 Pages

Scroll/Zoom	100%

nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

Trang chủ	http://www.st.com

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64 / 110 page

PSD835G2

PSD8XX Family

The

PSD4000

Functional

Blocks

(cont.)

DATA OUT

REG.

ADDRESS

EXT. CS (PORT F)

ENABLE PRODUCT TERM (.OE)

ALE

READ MUX

CONTROL REG.

DIR REG.

ENABLE OUT

CPLD INPUT (PORT F)

ISP OR BATTERY BACK-UP (PORT E)

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT PIN

DATA OUT

ADDRESS

A[ 7:0] OR A[15:8]

CONFIGURATION

BIT

Figure 28. Ports E, F and G Structure

9.4.8 Port F – Functionality and Structure

Port F can be configured to perform one or more of the following functions:

t MCU I/O Mode

t CPLD Output – external chip select ECS[7:0] can be connected to Port F (or Port C).

t CPLD Input – as direct input ot the CPLD array.

t Address In – additional high address inputs. Direct input to the CPLD array, no Input

Micro

⇔Cells latching is available.

t Latched Address Out – Provide latched address out per Table 29.

t Slew Rate – pins can be set up for fast slew rate.

t Data Port – connected to D[7:0] when Port F is configured as Data Port for a

non-multiplexed bus.

t Peripheral I/O Mode

9.4.9 Port G – Functionality and Structure

Port G can be configured to perform one or more of the following functions:

t MCU I/O Mode

t Latched Address Out – provide latched address out per Table 29.

t Open Drain – pins can be configured in Open Drain Mode

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