PSD835G2-70UI datasheet(69/110 Pages) STMICROELECTRONICS

69 / 110 page

PSD8XX Family

PSD835G2

APD

ALE

Enable Bit

PD Polarity

ALE Level

APD Counter

Not Counting

Pulsing

Not Counting

Counting (Generates PDN after 15 Clocks)

Table 28. APD Counter Operation

The

PSD835G2

Functional

Blocks

(cont.)

9.5.2 Other Power Saving Options

The PSD835G2 offers other reduced power saving options that are independent of the

Power Down Mode. Except for the SRAM Standby and CSI input features, they are

enabled by setting bits in the PMMR0 and PMMR2 registers.

9.5.2.1 Zero Power PLD

The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0.

By setting the bit to “1”, the Turbo mode is disabled and the PLDs consume Zero Power

current when the inputs are not switching for an extended time of 70 ns. The propagation

delay time will be increased after the Turbo bit is set to “1” (turned off) when the inputs

change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a “0”

(turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD’s D.C.

power, AC power, and propagation delay. Refer to AC/DC spec for PLD timings.

Note: Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power

consumption.

9.5.2.2 SRAM Standby Mode (Battery Backup)

The PSD835G2 supports a battery backup operation that retains the contents of the SRAM

in the event of a power loss. The SRAM has a Vstby pin (PE6) that can be connected to

an external battery. When VCC becomes lower than Vstby then the PSD will automatically

connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is

typically 0.5 µA. The SRAM data retention voltage is 2 V minimum. The battery-on

indicator (Vbaton) can be routed to PE7. This signal indicates when the VCC has dropped

below the Vstby voltage and that the SRAM is running on battery power.

9.5.2.3 The CSI Input

Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal

selects and enables the internal Flash, Boot Block, SRAM, and I/O for read or write

operations involving the PSD835G2. A high on the CSI pin will disable the Flash memory,

Boot Block, and SRAM, and reduce the PSD power consumption. However, the PLD and

I/O pins remain operational when CSI is high. Note: there may be a timing penalty when

using the CSI pin depending on the speed grade of the PSD that you are using. See the

timing parameter tSLQV in the AC/DC specs.

9.5.2.4 Input Clock

The PSD4000 provides the option to turn off the CLKIN input to the PLD to save AC

power consumption. The CLKIN is an input to the PLD AND array and the Output

Micro

⇔Cells. During Power Down Mode, or, if the CLKIN input is not being used as part of

the PLD logic equation, the clock should be disabled to save AC power. The CLKIN will be

disconnected from the PLD AND array or the Micro

⇔Cells by setting bits 4 or 5 to a “1” in

PMMR0.

9.5.2.5 MCU Control Signals

The PSD835G2 provides the option to turn off the address input (A7-0) and input control

signals (CNTL0-2, ALE, and DBE) to the PLD to save AC power consumption. These

signals are inputs to the PLD AND array. During Power Down Mode, or, if any of them are

not being used as part of the PLD logic equation, these control signals should be disabled

to save AC power. They will be disconnected from the PLD AND array by setting bits 0, 2,

3, 4, 5, and 6 to a “1” in the PMMR2.

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