PSD835G2-70UI datasheet(87/110 Pages) STMICROELECTRONICS

87 / 110 page

PSD8XX Family

PSD835G2

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VCC

Supply Voltage

All Speeds

3.0

3.6

VIH

High Level Input Voltage

3.0 V < VCC < 3.6 V

.7 VCC

VCC +.5

VIL

Low Level Input Voltage

3.0 V < VCC < 3.6 V

–.5

0.8

VIH1

Reset High Level Input Voltage

(Note 1)

.8 VCC

VCC +.5

VIL1

Reset Low Level Input Voltage

(Note 1)

–.5

.2 VCC –.1

VHYS

Reset Pin Hysteresis

0.3

VLKO

VCC Min for Flash Erase and Program

1.5

2.3

VOL

Output Low Voltage

IOL = 20 µA, VCC = 3.0 V

0.01

0.1

IOL = 4 mA, VCC = 3.0 V

0.15

0.45

VOH

Output High Voltage Except VSTBY On

IOH = –20 µA, VCC = 3.0 V

2.9

2.99

IOH = –1 mA, VCC = 3.0 V

2.7

2.8

VOH

Output High Voltage VSTBY On

IOH

= 1 µA

VSBY – 0.8

VSBY

SRAM Standby Voltage

2.0

VCC

ISBY

SRAM Standby Current (VSTBY Pin)

VCC = 0 V

0.5

µA

IIDLE

Idle Current (VSTBY Pin)

VCC > VSBY

–0.1

0.1

µA

VDF

SRAM Data Retention Voltage

Only on VSTBY

ISB

Standby Supply Current

CSI >VCC –0.3 V

100

µA

for Power Down Mode

(Notes 2 and 3)

ILI

Input Leakage Current

VSS < VIN < VCC

–1

±.1

µA

ILO

Output Leakage Current

0.45 < VIN < VCC

–10

± 5

µA

Output Current

Refer to IOL and IOH in

the VOL and VOH row

ZPLD_TURBO = OFF,

f = 0 MHz (Note 3)

0mA

PLD Only

ZPLD_TURBO = ON,

ICC (DC)

Operating

f = 0 MHz

200

400

µA/PT

(Note 5)

Supply Current

During FLASH

FLASH

Write/Erase Only

Read Only, f = 0 MHz

SRAM

f = 0 MHz

PLD AC Base

(Note 4)

Figure 32a

ICC (AC)

FLASH

(Note 5)

AC Adder

1.5

2.0

mA/MHz

SRAM AC Adder

0.8

1.5

mA/MHz

PSD835G2 DC Characteristics (3.0 V to 3.6 V Versions) Advance Information

NOTES: 1. Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC.

2. CSI deselected or internal PD mode is active.

3. PLD is in non-turbo mode and none of the inputs are switching.

4. Refer to Figure 31a for PLD current calculation.

5. IO = 0 mA.

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