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PSD835G2-70UI bảng dữ liệu(PDF) 33 Page - STMicroelectronics

tên linh kiện PSD835G2-70UI
Giải thích chi tiết về linh kiện  Configurable Memory System on a Chip for 8-Bit Microcontrollers
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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PSD835G2-70UI bảng dữ liệu(HTML) 33 Page - STMicroelectronics

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PSD8XX Family
PSD835G2
32
The
PSD835G2
Functional
Blocks
(cont.)
9.1.5 Memory ID Registers
The 8-bit read only memory status registers are included in the CSIOP space. The user
can determine the memory configuration of the PSD device by reading the Memory ID0
and Memory ID1 registers. The content of the registers are defined as follow:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
Memory_ID0 Register
Main Flash Size
F_size3
F_size2
F_size1
F_size0
(Bit)
0
0
0
0
none
0
0
0
1
256K
0
0
1
0
512K
0
011
1M
0
100
2M
0
101
4M
0
110
8M
Bit Definition
SRAM Size
S_size3
S_size2
S_size1
S_size0
(Bit)
0
0
0
0
none
0
001
16K
0
010
32K
0
011
64K
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
**
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
Memory_ID1 Register
*Not used bit should be set to zero.
Boot Block Size
B_size3
B_size2
B_size1
B_size0
(Bit)
0
0
0
0
none
0
0
0
1
128K
0
0
1
0
256K
0
0
1
1
512K
Bit Definition
B_type1
B_type0
Boot Block Type
0
0
Flash
0
1
EEPROM



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