PSD835G2-70UI datasheet(47/110 Pages) STMICROELECTRONICS

47 / 110 page

PSD8XX Family

PSD835G2

The

PSD835G2

Functional

Blocks

(cont.)

Configuration

80C251

Connecting to

Page Mode

Read/Write

PSD835G2

Pins

CNTL0

Non-Page Mode, 80C31 compatible

CNTL1

[7:0] multiplex with D[7:0}

PSEN

CNTL2

CNTL0

Non-Page Mode

PSEN only

CNTL1

[7:0] multiplex with D[7:0}

CNTL0

Page Mode

PSEN only

CNTL1

[15:8] multiplex with D[7:0}

CNTL0

Page Mode

CNTL1

[15:8] multiplex with D[7:0}

PSEN

CNTL2

Table 15. 80C251 Configurations

9.3.3.3 80C51XA

The Philips 80C51XA microcontroller family supports an 8- or 16-bit multiplexed bus that

can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are

multiplexed with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed

with data bits D[7:0].

The 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 22).

The 80C51XA improves bus throughput and performance by executing Burst cycles for

code fetches. In Burst Mode, address A19-4 are latched internally by the PSD835G2, while

the 80C51XA changes the A3-0 lines to fetch up to 16 bytes of code. The PSD access

time is then measured from address A3-A0 valid to data in valid. The PSD bus timing

requirement in Burst Mode is identical to the normal bus cycle, except the address setup

and hold time with respect to ALE does not apply.

9.3.3.4 68HC11

Figure 23 shows an interface to a 68HC11 where the PSD835G2 is configured in 8-bit

multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR

signals for external devices.

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