ORSPI4 datasheet(171/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

171

30B2A

[0]

TX_INT_B

Signals that an enabled interrupt has come from TX DPRAM FIFOs for SPI4

core B. This is cleared when read and will only reassert when the underlying

event goes away and comes back.

[1]

RX_INT_B

Signals that an enabled interrupt has come from RX DPRAM FIFOs for SPI4

core B. This is cleared when read and will only reassert when the underlying

event goes away and comes back.

[2]

TX_INT_A

Signals that an enabled interrupt has come from TX DPRAM FIFOs for SPI4

core A. This is cleared when read and will only reassert when the underlying

event goes away and comes back.

[3]

RX_INT_A

Signals that an enabled interrupt has come from RX DPRAM FIFOs for SPI4

core B. This is cleared when read and will only reassert when the underlying

event goes away and comes back.

[4]

BANK_3_INT

Signals that an enabled interrupt has come from DPRAM bank 3 FIFOs (or

both SPI4 blocks, both TX and RX ﬂags). This is cleared when read and will

only reassert when the underlying event goes away and comes back.

[5]

BANK_2_INT

Signals that an enabled interrupt has come from DPRAM bank 2 FIFOs (or

both SPI4 blocks, both TX and RX ﬂags). This is cleared when read and will

only reassert when the underlying event goes away and comes back.

[6]

BANK_1_INT

Signals that an enabled interrupt has come from DPRAM bank 1 FIFOs (or

both SPI4 blocks, both TX and RX ﬂags). This is cleared when read and will

only reassert when the underlying event goes away and comes back.

[7]

BANK_0_INT

Signals that an enabled interrupt has come from DPRAM bank 0 FIFOs (or

both SPI4 blocks, both TX and RX ﬂags). This is cleared when read and will

only reassert when the underlying event goes away and comes back.

30B2B

[0:7]

COM_SPARE_S

Spare common status bits

Embedded Control Memory Access (31000-31FFF)

31000

[0:7]

data[7:0]

Embedded control memories are accessed when register addresses 3100-

31FFF are written or read. The address passed to the embedded memories

is the lower 12 bits of the register address. Writing to a register address in

this range causes data to be transferred to the selected embedded memo-

ries. More than one memory can be written with a single operation by having

multiple select bits active. The select bits are 30917 and 30A17 registers.

Reading from a register address in this range causes the data in the mem-

ory selected to appear. The following priority rules apply to the selection of

which memory is read from.

(1) 30917 bits take precedence over bits in the 30A17 register.

(2) lower bit numbers take precedence over higher bit numbers within a reg-

ister.

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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