ORSPI4 datasheet(170/263 Pages) LATTICE

170 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

170

Common Control Registers (Read and Write)

30B20

[0:3]

Reserved

[4]

HARD_RESET_FC

Hard reset for SERDES block. When set to 1, disabled SERDES logic by

resetting it. Same functionality as interface signal FPGA_RESET_FC

[5]

SOFT_RESET_MC

Software reset for Memory Controller block

[6]

SOFT_RESET_S4A

Software reset for SPIA block

[7]

SOFT_RESET_S4B

Software reset for SPIB block

30B21

[0:6]

COM_SPARE_C

Spare common control bits

[7]

FORCE_INT

Force all the enabled status and interrupt bits

Common Status Registers (Read and Write)

30B28

[0:7]

Reserved

30B29

[0]

SERDES_INT

Signals that an enabled interrupt has come from the SERDES. This is

cleared when read and will only reassert when the underlying event goes

away and comes back.

[1]

MEM_CTRL2_INT

Signals that an enabled interrupt has come from the Memory Controller

other than the FIFOs. This is cleared when read and will only reassert when

the underlying event goes away and comes back.

[2]

MEM_CTRL1_INT

Signals that an enabled interrupt has come from the Memory Controller

FIFOs. This is cleared when read and will only reassert when the underlying

event goes away and comes back.

[3]

DPRAM_INT

Signals that an enabled interrupt has come from one of the DPRAM FIFO

banks. This is cleared when read and will only reassert when the underlying

event goes away and comes back.

[4]

SPI_B_COR2_INT

Signals that an enabled interrupt has come from the register 30A1D. This is

cleared when read and will only reassert when the underlying event goes

away and comes back.

[5]

SPI_B_COR1_INT

Signals that an enabled interrupt has come from register 30A1C. This is

cleared when read and will only reassert when the underlying event goes

away and comes back.

[6]

SPI_A_COR2_INT

Signals that an enabled interrupt has come from register 3091D. This is

cleared when read and will only reassert when the underlying event goes

away and comes back.

[7]

SPI_A_COR1_INT

Signals that an enabled interrupt has come from register 3091C. This is

cleared when read and will only reassert when the underlying event goes

away and comes back.

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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