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ORSPI4 bảng dữ liệu(PDF) 100 Page - Lattice Semiconductor |
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ORSPI4 bảng dữ liệu(HTML) 100 Page - Lattice Semiconductor |
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100 / 263 page ![]() Lattice Semiconductor ORCA ORSPI4 Data Sheet 100 Figure 44. Low-Speed Near End Loopback (Excluding High-Speed Blocks) SPI4 Error Insertion Capabilities The SPI4 blocks support the following error insertion options for testing: • DIP-4 odd parity is calculated over data and control words on the TX side. Under software control, DIP-4 errors can be forced by inverting the DIP-4 parity bits. This is done by setting TX_FORCE_DIP4_ERR bit to ‘1’ (Address 30915 in SPIA and 30A15 in SPIB). • DIP-2 odd parity is calculated over the status frames on the RX side. Under software control, DIP-2 errors can be forced by inverting the DIP-2 parity bits. This feature can be enabled by setting RX_FORCE_DIP2_ERR to ‘1’ (Address 30915 in SPIA and 30A15 in SPIB). SPI4 Status Reporting Capabilities The following status information will be reported through status registers. Most status registers also cause inter- rupts. The interrupts can be masked by the corresponding interrupt enables. • DIP-4, DIP-2 errors (These cause interrupts). The associated register status bits are: – RX_ALGN_OFF_STS, TX_STATUS_LOF_STS, RX_DIP4_ERR_STS, TX_DIP2_ERR_STS • DIP-4, DIP-2 error counters. These are 8-bit counters. The status registers are: – RX_DIP4_ERR_CNT, TX_DIP2_ERR_CNT • Deskew status and error from high-speed RX side. These cause an interrupt. The associated register status bits are: – RX_DSKW_DONE_STS, RX_DSKW_ERR_STS – DPRAM FIFO overruns and underruns (RX and TX DPRAM memories). These can cause an interrupt. – SPIA or SPIB Receive PLL Loss of lock indicator. The associated register bit is –RX_PLL_LOL_STS TDAT[15:0] TCTL TDCLK SPI4 I/F TDO TREFCLK TSTAT[1:0] TSCLK RDAT[15:0] RCTL RDCLK RDI RSTAT[1:0] RSCLK TDP 128-bit data+ctl b TSP clk DPRAMs + associated logic Port write Sequencer TX RDP RSP DPRAMs + associated logic Port Status Sequencer clk 128-bit data+ctl clk RX Embedded Core |
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