 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ORSPI4 bảng dữ liệu(PDF) 1 Page - Lattice Semiconductor |
|
|
|||||||||||||||||||||||||||||
ORSPI4 bảng dữ liệu(HTML) 1 Page - Lattice Semiconductor |
|
|
1 / 263 page  ORCA ® ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC October 2007 Data Sheet © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 ORSPI4_06 Embedded SPI4 Core Features ■ OIF-SPI4-02.0 compliant interfaces ■ Dynamic timing receive interface: • Full bandwidth up to 450 MHz DDR (900 Mbits/s) for all speed grades. • Bit de-skewing up to 16 phases of the clock • Capable of aligning bit-to-bit skews as large as ±1 bit periods ■ Static timing receive interface: • Speeds up to 325 MHz DDR (650 Mbits/s), for all speed grades, including Quarter-Rate mode • Clock aligned or clock centered modes sup- ported ■ DIP-4 and DIP-2 parity generation and checking ■ Transmit Interface: • Speeds up to 450 MHz DDR (900 Mbits/s) • Dedicated LVDS transmit interface for improved data eye integrity • Automatic idle insertion ■ 256 logical ports: • Embedded Calendar-based sequence port poll- ing mechanism and bandwidth allocation. Shadow Calendar support for smooth transition to new Calendar • Up to 32 independent TX and 32 independent RX buffers per SPI4 interface internally. Various aggregation modes to support 1 to 32 separate embedded buffers per TX and RX • Up to 4 independent TX and 4 independent RX clock domain transfers to the FPGA logic ■ FIFO status support modes: • 1/4 rate LVTTL or 1/4 rate LVDS • Automatic status handling or optionally under user control. Credit calculations based on burst size and status are also handled automatically ■ Configuration options as suggested in the OIF- SPI4-02.0 standard • Configures parameters such as maximum burst size, calendar length, main and shadow calen- dars (1K deep each), length of training sequence etc. ■ Simple FIFO interface to the FPGA logic • Provides ease of design and efficient clock domain transfers ■ Loopback modes provided for system- and chip-level debug ■ Embedded 32-bit internal system bus plus 4-bit parity • Interconnects FPGA logic, microprocessor inter- face (MPI), embedded RAM blocks, and embed- ded core blocks • Includes built-in system registers that act as the control and status center for the device ■ Low power operation. • Full-rate SPI4.2 interfaces running at 450 MHz DDR (900 Mbits/sec) with dynamic alignment consumes 1.5 W of power or less. More efficient than FPGAs with soft-IP SPI4 solutions which consume in excess of 10 W. ■ Programmable Minburst capability with selectable burst values ranging from 16 to 240. ■ Interoperability demonstrated with ORSPI4 partners. Embedded SERDES Core Features ■ Quad 600 Mbits/s to 3.7 Gbits/s SERDES: • IEEE 802.3ae XAUI (Link State Machine & Alignment FIFOs embedded) • ANSI X3.230:1994 1G/2G FC-compliant (Link State Machine & Alignment FIFOs embedded) • Proven performance (same SERDES used in ORT82G5/ORT42G5 FPSCs) Embedded Memory Controller Features ■ High Performance Memory Controller for interface to external buffer memory • Required for Layer 2 data buffering • QDR II memory interface: – 36-bit Input and 36-bit Output bus, 18-bit address – 175 MHz clock rates – 20+ Gbits/s bandwidth – Supports 2- or 4-word burst mode – Simple FIFO interface to FPGA – Integrated PLL for optimized performance – Proven performance with multiple memory suppliers Note: The term SPI4 refers to OIF SPI-4.2 throughout this document Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on a single chip. |
Số phần tương tự - ORSPI4 |
|
Mô tả tương tự - ORSPI4 |
|
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
