ORSPI4 datasheet(48/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Partitioning of the Dual Port RAMs is done through customer programmable registers. Table 8 below shows Regis-

ter Settings for Aggregation Mode and Partition Size.

Table 8. Register Settings for Aggregation Mode and Partition Size.

DPRAM Aggregation

Mode

Address 30903 (SPIA),

30A30 (SPIB)

Virtual FIFO Partition Size

Address 30927 (SPIA),

30A27 (SPIB)

Conﬁguration

DPRAM 0

(register Bits 0:1) = 00

32-bit data width, partition size 1

32-bit data width, partition size 2

32-bit data width, partition size 4

32-bit data width, partition size 8

64-bit data width, partition size 1

64-bit data width, partition size 2

64-bit data width, partition size 4

64-bit data width, partition size 8

128-bit data width, partition size 1

128-bit data width, partition size 2

128-bit data width, partition size 4

128-bit data width, partition size 8

DPRAM 1

(Register Bits 2:3) = 00

32-bit data width, partition size 1

32-bit data width, partition size 2

32-bit data width, partition size 4

32-bit data width, partition size 8

64-bit data width, partition size 1

64-bit data width, partition size 2

64-bit data width, partition size 4

64-bit data width, partition size 8

128-bit data width, partition size 1

128-bit data width, partition size 2

128-bit data width, partition size 4

128-bit data width, partition size 8

DPRAM 2

(Register Bits 4:5) = 00

32-bit data width, partition size 1

32-bit data width, partition size 2

32-bit data width, partition size 4

32-bit data width, partition size 8

64-bit data width, partition size 1

64-bit data width, partition size 2

64-bit data width, partition size 4

64-bit data width, partition size 8

128-bit data width, partition size 1

128-bit data width, partition size 2

128-bit data width, partition size 4

128-bit data width, partition size 8

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