ORSPI4 datasheet(96/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 41. Read Timing with ERR Asserted - 128-Bit Mode

Special Operating Modes

Static Capture Mode

The ORSPI4 receiver supports both dynamic and static capture of data at the high-speed SPI4 interface. All the

operating modes (32-bit, 64-bit and 128-bit) are independent of the type of data capture. They can operate in either

static or dynamic capture mode. The choice of static vs. dynamic alignment depends on the SPI4 data rates. The

static data capture is valid in the frequency range 400-700 Mbps. It also reduces the power dissipation of the

device. The following control signals are relevant to enable static data capture:

SPI4_LOW_SPEED_DATA_SEL: This is a software register control bit (Address 30915 in SPIA and 30A15 in

SPIB). When set to ‘0’, the dynamic alignment circuit is held in a reset state and the static alignment mode is

enabled.

SPI_DATM_A or SPI_DATM_B: This is a control signal from the FPGA. When set to ‘1’, this gives the user the

option to skew the RDCLK with respect to the SPI4 data bus RDAT on the bus by choosing delay taps through the

control bits SPI_DLYTAP_A[2:0] of SPI_DLYTAP_B[2:0]. When set to ‘0’, RDCLK is automatically centered on-chip

to the input data bus RDAT.

Quarter-Rate Mode

SPIA_RX128_CLK

….

SPIA_RX128_RD

SPIA_RX128_FIFO_EMPTY

SPIA_RX128_DATA

2 cycles after read

enable

SPIA_RX128_SOP

SPIA_RX128_EOP

FIFO size = 64 locations.

SPIA_RX128_ADDR

ASTOP_ON_EOP

SPIA_RX128_BE

SPIA_RX128_ERR

hffff

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