ORSPI4 datasheet(66/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

FPGA Sourced Data and Control

In this mode, the FPGA sends data into the embedded core relative to the rising edge of it’s own clock as well as

providing the clock for the embedded core. The embedded core uses the FPGA clock to register all input data and

control signals. Figure 27 shows the Worst Case Slow and Worst Case Fast propagation delays for the FPGA input

data and control signals as well as the clock signal.

For guaranteed performance it is important that all input signals from the FPGA be registered before being sent

into the embedded core.

Clocking Schemes and Timing Diagrams - Transmit DPRAM Interface

Figure 27. Data: SPI[A,B]_DATA/SOP/EOP/BE/ERR/PORT/WE/ADDR/SPI[A,B]_TXk_WD_CNT_RST

/LINK_DIS

Clock: SPI[A,B]_k_CLK_[3:0]; k=32, 64,128

Embedded Core Sourced Status

The embedded core sources port and status information relative to a buffered version of the externally provided ref-

erence clock (TREFCLK). The FPGA receives both the status information and clock, and can use the provided

clock to synchronize all status information for it’s own use. Figure 28 shows the Worst Case Slow and Worst Case

Fast propagation delays for the embedded core output status signals as well as the clock signal.

With the given timing delays the FPGA logic can either immediately register the provided status information or, if

required, implement some combinatorial logic function before registering the information.

3.5/0.5 ns

1.5/0.5 ns

4.81 / 1.18 ns

FPGA

Embedded Core

1.36/ 0.47 ns

Setup = 2.6 ns

Hold = - 0.32 ns

NOTE: Delays represent average max/min values, not absolute values

Delay

Buffer

Delay

Actual delay values are used by

ispLEVER

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