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5-2

System Reset

5.2

Hardware Reset Timing

This section describes the timing of the hardware reset signal.

The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase

2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is

found active (low level) the internal reset procedure is started. It needs two complete machine

cycles to put the complete device to its correct reset state, i.e. all special function registers contain

their default values, the port latches contain 1’s etc. The RESET signal must be active for at least

two machine cycles; after this time the SAB-C511/513 remains in its reset state as long as the signal

is active. When the signal goes inactive this transition is recognized in the following state 5 phase

2 of the machine cycle. Then the processor starts its address output (when configured for external

ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin

ALE occurs.

Figure 5-12 shows this timing for a configuration with EA = 0 (external program memory). Thus,

between the release of the RESET signal and the first falling edge at ALE there is a time period of

at least one machine cycle but less than two machine cycles.

Figure 5-12

CPU Timing after Reset

MCT02092

P1 P2

PCL

OUT

PCH

OUT

PCH

OUT

One Machine Cycle

RESET

ALE

Inst.

OUT

PCL

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