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On-Chip Peripheral Units

Semiconductor Group

6-1

On-Chip Peripheral Components

6.1

Parallel I/O

The SAB-C511/513 has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while

ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when

configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled

low. Port 0 will float when configured as input.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external

memory. In this application, port 0 outputs the low byte of the external memory address, time

multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory

address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR

contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET.

Port 1 pins used for SSC outputs are true push-pull outputs. When used as SSC inputs they float

(no pull-up).

6.1.1 Port Structures

Each port bit consists of a latch, an output driver(s) and an input buffer. Read and write accesses

to the I/O ports P0, P1, P2 and P3 are performed via the corresponding special function registers.

Figure 6-13 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each

of the four I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop,

which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU.

Both the output of the latch as well as the actual state of the port pins can be read, depending on

the instruction used for accessing the port.

Figure 6-13

Basic Structure of a Port Circuitry

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