C511 datasheet(83/128 Pages) SIEMENS

83 / 128 page

Semiconductor Group

6-50

On-Chip Peripheral Units

Note: SSCCON must be programmed only when the SSC is idle. Modifying the contents of

SSCCON while a transmission is in progress will corrupt the current transfer and will lead to

unpredictable results.

CPHA

Clock Phase

This bit controls in conjunction with the CPOL bit controls which clock edges are

used for sample and shift

CPHA=0 : The first clock edge of SCLK is used to sample the data, the second

to shift the next bit out at STO.

In master mode the transmitter will provide the first data bit on STO

immediately after the data was written into the STB register.

In slave mode the transmitter (if enabled via TEN) will shift out the

first data bit with the falling edge of SLS .

CPHA=1 : The first data bit is shifted out with the first clock edge of SCLK and

sampled with the second clock edge

BRS2,

BRS1, BRS0

Baudrate Selection Bits

These bits select one of the possible divide factors for generating the baudrate out

of the micrcontroller clock rate fosc . The baudrate is defined by .

for BRS (2-0)

≠ 0

Bit

Function

Baudrate

fosc

Dividefactor

--------------------------------

fosc

•

BRS 2

–

()

------------------------------------

BRS(2-0)

Divide

Factor

Example:

Baudrate for fosc

= 7.68 MHz

reserved

960 kBaud

480 kBaud

240 kBaud

120 kBaud

128

60 kBaud

256

30 kBaud

512

15 kBaud

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