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C511 bảng dữ liệu(PDF) 49 Page - Siemens Semiconductor Group |
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C511 bảng dữ liệu(HTML) 49 Page - Siemens Semiconductor Group |
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49 / 128 page ![]() Semiconductor Group 6-16 On-Chip Peripheral Units 6.2.1 Timer/Counter 0 and 1 Timer / counter 0 and 1 of the SAB-C511/513 family components are fully compatible with timer / counter 0 and 1 of the 8051 microcontroller and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is split into one 8-bit timer/counter and one 8-bit timer when programmed to this mode. Timer/counter 1 set to this mode will simply hold its count. The effect is the same as setting TR1 = 0, disabling the counter. The external inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/ counter 1) which may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two special function registers TCON and TMOD. In the following descriptions the symbols TH0 and TL0 are used to specify the high-byte and the low-byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicity noted, this applies also to timer 1. Special Function Register TCON (Address 88H) Reset Value : 00H Bit Function TR0 Timer 0 run control bit. Set/cleared by software to turn timer/counter 0 ON/OFF. TF0 Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR1 Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 ON/OFF. TF1 Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TF1 TR1 TF0 TR0 88H TCON Bit No. 7 65 43 21 0 MSB LSB IE1 IT1 IE0 IT0 These bits are not used in controlling timer/counter 0 and 1. |
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