NRF52810-QFAA-R datasheet(373/483 Pages) NORDIC

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Peripherals

START

CPU

ENDTX

ORC

CSN

SCK

MOSI

m-2

m-1

MISO

ENDRX

Figure 98: SPI master transaction

6.18.2 Master mode pin configuration

The SCK, MOSI, and MISO signals associated with the SPI master are mapped to physical pins according to

the configuration specified in the PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively.

The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as long as the

SPI master is enabled, and retained only as long as the device is in ON mode. PSEL.SCK, PSEL.MOSI and

PSEL.MISO must only be configured when the SPI master is disabled.

To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral

as described in GPIO configuration on page 373 prior to enabling the SPI. This configuration must be

retained in the GPIO for the selected IOs as long as the SPI is enabled.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in

unpredictable behavior.

SPI master signal

SPI master pin

Direction

Output value

SCK

As specified in PSEL.SCK

Output

Same as CONFIG.CPOL

MOSI

As specified in PSEL.MOSI

Output

MISO

As specified in PSEL.MISO

Input

Not applicable

Table 74: GPIO configuration

6.18.3 EasyDMA

The SPI master implements EasyDMA for reading and writing of data packets from and to the DATA RAM

without CPU involvement.

RXD.PTR and TXD.PTR point to the RXD buffer (receive buffer) and TXD buffer (transmit buffer)

respectively, see SPIM — SPI master with EasyDMA on page 371. RXD.MAXCNT and TXD.MAXCNT

specify the maximum number of bytes allocated to the buffers. The SPI master will automatically

stop transmitting after TXD.MAXCNT bytes have been transmitted and RXD.MAXCNT bytes have been

4430_161 v1.0

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