NRF52810-QFAA-R datasheet(371/483 Pages) NORDIC

371 / 483 page

Peripherals

Symbol

Description

Min.

Typ.

Max.

Units

SNDR

Peak signal to noise and distortion ratio, differential mode,

12-bit resolution, 1/1 gain, 3 µs acquisition time, crystal

HFCLK, 200 ksps

SFDR

Spurious free dynamic range, differential mode, 12-bit

resolution, 1/1 gain, 3 µs acquisition time, crystal HFCLK,

200 ksps

dBc

RLADDER

Ladder resistance

160

kΩ

6.17.13 Performance factors

Clock jitter, affecting sample timing accuracy, and circuit noise can affect ADC performance.

Jitter can be between START tasks or from START task to acquisition. START timer accuracy and startup

times of regulators and references will contribute to variability. Sources of circuit noise may include CPU

activity and the DC/DC regulator. Best ADC performance is achieved using START timing based on the

TIMER module, HFXO clock source, and Constant Latency mode.

6.18 SPIM — Serial peripheral interface master with

EasyDMA

The SPI master can communicate with multiple slaves using individual chip select signals for each of the

slave devices attached to a bus.

Listed here are the main features for the SPIM

• SPI mode 0-3

• EasyDMA direct transfer to/from RAM for both SPI Slave and SPI Master

• Individual selection of IO pin for each SPI signal

MISO

MOSI

RXD-1

TXD+1

EasyDMA

RXD.PTR

TXD.PTR

buffer[0]

buffer[1]

buffer[RXD.MAXCNT-1]

RAM

buffer[0]

buffer[1]

buffer[TXD.MAXCNT-1]

PSEL.MOSI

GPIO

PSEL.MISO

PSEL.SCK

SCK

SPIM

TXD buffer

RXD buffer

Figure 97: SPIM — SPI master with EasyDMA

4430_161 v1.0

371

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