S2-LPS datasheet(43/73 Pages) STMICROELECTRONICS

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Figure 14. SPI read sequence

Figure 15. SPI command sequence

Concerning the first byte, the MSB is an A/C bit (address/commands: 0 indicates that the following byte is an

address, 1 indicates that the following byte is a command code), while the LSB is a W/R bit (write/read: 1

indicates a read operation). All other bits must be zero.

Read and write operations are persistently executed while CSn is kept active (low), the address is automatically

incremented (burst mode).

Accessing the FIFO is done as usual with the read and write commands, by putting, as address, the code 0xFF.

Burst mode is available to access the sequence of bytes in the FIFO. Clearly, RX-FIFO is accessed with a read

operation, TX-FIFO with a write operation.

7.2

Interrupts

In order to notify the MCU of a certain number of events an interrupt signal is generated on a selectable GPIO.

The following events trigger an interrupt to the MCU:

Table 47. Interrupts list

Bit

Events group

Interrupt event

Packet oriented

RX data ready

RX data discarded (upon filtering)

TX data sent

Max. re-TX reached

CRC error

TX FIFO underflow/overflow error

RX FIFO underflow/overflow error

S2-LPS

Interrupts

DS13831 - Rev 1

page 43/73

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