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S2-LPS bảng dữ liệu(PDF) 36 Page - STMicroelectronics

tên linh kiện S2-LPS
Giải thích chi tiết về linh kiện  Ultra-low power, high performance, sub-1 GHz transceiver
PDF  73 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

S2-LPS bảng dữ liệu(HTML) 36 Page - STMicroelectronics

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State code(1)
State name
Digital LDO
SPI
XTAL
RF synth.
Wake-up timer
0x01
SLEEP_A
On
Off
Off
On
0x03
SLEEP_B
On
Off
Off
On
0x00
READY
On
On
Off
Do not care
0x0C
LOCK
On
On
On
Do not care
0x30
RX
On
On
On
Do not care
0x5C
TX
On
On
On
Do not care
0x50
SYNTH_SETUP
On
On
On
Do not care
1. Other codes are invalid and are an indication of an error condition due to bad register configuration and/or hardware issue in
the application board hosting.
Commands are used in the S2-LPS to change the operating mode and to use its functionality. A command is sent
on the SPI interface and may be followed by any other SPI access without pulling CSn high. A command code is
the second byte to be sent on the MOSI pin (the first byte must be 0x80). The commands are immediately valid
after SPI transfer completion (no need for any CSn positive edge).
5.1
Command list
Table 42. Commands
Command code
Command name
State for
execution
Description
0x60
TX
READY
Send the S2-LPS to TX state for transmission
0x61
RX
READY
Send the S2-LPS to RX state for reception
0x62
READY
STANDBY, SLEEP,
LOCK
Go to READY state
0x63
STANDBY
READY
Go to STANDBY state
0x64
SLEEP
READY
Go to SLEEP state
0x65
LOCKRX
READY
Go to LOCK state by using the RX configuration of the
synthesizer
0x66
LOCKTX
READY
Go to LOCK state by using the TX configuration of the
synthesizer
0x67
SABORT
TX, RX
Exit from TX or RX states and go to READY state
0x68
LDC_RELOAD
ANY
Reload the LDC timer with a pre-programmed value stored
in registers
0x70
SRES
ANY
Reset the S2-LPS state machine and registers values
0x71
FLUSHRXFIFO
All
Clean the RX FIFO
0x72
FLUSHTXFIFO
All
Clean the TX FIFO
0x73
SEQUENCE_UPDA TE
ANY
Reload the packet sequence counter with the value stored in
register
5.2
State transaction response time
Table 43. Response time
Initial state
Final state
Response time [µs]
SHUTDOWN
READY
500
S2-LPS
Command list
DS13831 - Rev 1
page 36/73



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