S2-LPS datasheet(18/73 Pages) STMICROELECTRONICS

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Block description

4.1

Power management

The S2-LPS integrates a high efficiency step-down converter cascaded with LDOs meant to supply both analog

and digital parts. However, an LDO directly fed by the external battery provides a controlled voltage to the data

interface block.

S2-LPS’s power management (PM) strategy, besides the basic functionality of providing different blocks with

proper supplies, faces two main constraints: the first one is to implement such a power distribution with maximum

efficiency, and the second one is to guarantee the isolation among critical blocks.

The efficiency target is obtained by using a switch mode power supply (SMPS) which converts the battery voltage

(1.8 V - 3.6 V) to a lower voltage (settable from 1.2 V to 1.8 V) with efficiency higher than 90%.

The SMPS output voltage can be controlled by the SET_SMPS_LVL field in the PM_CONF0 register. The relation

between the SET_SMPS_LVL and the VOUT of the SMPS is given by the following table:

Table 28. SMPS output voltage

SET_SMPS_LVL

SMPS output voltage

001b

1.2 V

010b

1.3 V

011b

1.4 V

100b

1.5 V

101b

1.6 V

110b

1.7 V

111b

1.8 V

The SMPS output voltage can be controlled in TX only or for both RX and TX according to the SMPS_LVL_MODE

bit of the PM_CONF1 register.

•

1: SMPS output level depends upon the value in PM_CONFIG register just in TX state, while in RX state it is

fixed to 1.4 V.

•

0: SMPS output level depends upon the value written in the PM_CONFIG0 register (SET_SMPS_LEVEL

field) both in RX and TX state.

The SMPS switching frequency is settable by the 2 registers PM_CONF3 and PM_CONF2.

If the KRM_EN is 0, then the digital divider by 4 enabled. In this case SMPS' switching frequency is:

Fsw=fdig4

(3)

If the KRM_EN is 1, the SMPS' switching frequency can be set by the KRM word according to the formula:

Fsw=Krmfdig215

(4)

fdigisthedigitaldomainfrequency(fXOifitis26MHz).

All the RX measurements reported in this datasheet have been taken with a SMPS frequency set to 1.56 MHz.

From the formula reported with fdig = 25 MHz, PM_CONF3 = 0x87, PM_CONF2 = 0xFC, the Fsw is 1.56. It is

possible to have a little improvement of the sensitivity reducing the SMPS switching frequency but having as

drawback a higher current consumption.

The isolation target is reached by using, for each critical block, a dedicated linear low-dropout regulator (LDO),

which provides typically 1.2 V output voltage, either from battery level or from SMPS level, depending from the

operating mode.

If the output of the LDO is 1.2 V the minimum value of the SMPS, Vout must be at least 100 mV higher than the

Vout of the LDO. This means that in HPM (SMPS+LDO) the minimum value of the SMPS_VOUT must be 1.3 V.

S2-LPS

Block description

DS13831 - Rev 1

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