S2-LPS datasheet(29/73 Pages) STMICROELECTRONICS

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4.4.5.6

RX timer management

The programmable RX timer used can be configured using quality indicator to avoid unwanted interruption during

a valid packet due to RX timer expiration. The quality indicators used to stop the RX timer are SQI, CS and

PQI. More specifically, AND or OR Boolean relationships among any of them can be configured, to suit user

application. In particular, it is required to include always SQI valid check, to avoid to stay in RX state for unlimited

time, if timeout is stopped but no valid SQI is detected (in such cases, the RX state can be left using a SABORT

command).

On timer expiration, reception aborts and the packet is discarded.

Table 38. RX timer stop condition configuration

RX_TIMEOUT_AND_OR_SELECT CS_TIMEOUT_MASK SQI_TIMEOUT_MASK

PQI_TIMEOUT_MASK

Description

The RX timeout never expires and the

reception ends at the reception of the

packet

The RX timeout cannot be stopped. It

starts at the RX state and at the end

expires

RSSI above threshold

SQI above threshold (default)

PQI above threshold

Both RSSI AND SQI above threshold

Both RSSI AND PQI above threshold

Both SQI AND PQI above threshold

ALL above threshold

RSSI OR SQI above threshold

RSSI OR PQI above threshold

SQI OR PQI above threshold

ANY above threshold

4.4.5.7

Receiver data modes

Direct modes are primarily intended to completely bypass the automatic packet handler, in order to give the user

maximum flexibility in the choice of frame formats. Specifically:

•

Direct through FIFO mode: the packet bytes are continuously received and written in the RX FIFO without

any processing. It is the responsibility of the microcontroller to avoid any overflow conditions on the RX

FIFO.

•

Direct through GPIO mode: the packet bits are continuously written to one of the GPIO pins without any

processing. To allow the synchronization of an external data sink, a data clock signal is also provided on one

of the GPIO pins. Data are updated by the device on the falling edge of such clock signal so the MCU must

read it during falling edge of CLK.

4.4.5.8

Receiver quality indicators

S2-LPS

Digital modulator

DS13831 - Rev 1

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