S2-LPS datasheet(3/73 Pages) STMICROELECTRONICS

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Detailed functional description

The S2-LPS fully supports antenna diversity with an integrated antenna switching control algorithm.

Transmitted/received data bytes are buffered in two different 128 bytes FIFOs (TX FIFO and RX FIFO),

accessible via SPI interface for host processing.

In addition, the reduced number of external components enables a cost effective solution permitting a compact

PCB footprint.

The S2-LPS targets volume applications like:

•

Sensors to Cloud

•

Smart metering

•

Home energy management systems

•

Wireless alarm systems

•

Smart home

•

Building automation

•

Industrial monitoring and control

Figure 1. Simplified S2-LPS block diagram

The receiver architecture is low-IF conversion, the received RF signal is amplified by a two-stage low-noise

amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). LNA and IF

amplifiers make up the RX front-end (RXFE) and have programmable gain. At IF, the ADCs digitalize the I/Q

signals. The demodulated data go to an external MCU either through the 128-byte RX FIFO, readable via SPI, or

directly using a programmable GPIO pin.

The transmitter part of the S2-LPS is based on direct synthesis of the RF frequency. The power amplifier (PA)

input is the LO generated by the RF synthesizer, while the output level can be configured between -30 dBm and

+14 dBm (+16 dBm in boost mode), at antenna level with 0.5 dB steps.

S2-LPS

Detailed functional description

DS13831 - Rev 1

page 3/73

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