R7KA8D2AFDCAC datasheet(78/292 Pages) RENESAS

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Table 2.35

Coremark and normal mode current, CPU0 Deep Sleep, CPU1 active. (DCDC mode and External VDD

mode)

Parameter

Symbol Typ

Max

Unit Test conditions

°C

105

°C

Supply

current*1*2

CPUCLK1 =

250 MHz

VSCR_1

VCL =

voltage

range 1

Coremark

Cache on

IDD

215

—

μA/

CPU0 = Deep Sleep

Graphics and ESWM power

domain off

CPUCLK0 = 1 GHz, MRICLK

= 250 MHz, MRPCLK = 15.6

MHz, ICLK = 250 MHz, PCLKA

= 15.6 MHz, PCLKB = 15.6

MHz, PCLKC = 15.6 MHz,

PCLKD = 15.6 MHz, PCLKE =

15.6 MHz, BCLK = 15.6 MHz

Cache off, executing

from ITCM

197

—

Cache off, executing

from SRAM

194

—

Cache off, executing

from MRAM

268

—

Normal

mode

All peripheral disabled,

Cache on, while (1)

code

201

—

All peripheral disabled,

Cache off, while (1)

code executing from

MRAM

264

—

CPUCLK1 =

200 MHz

VSCR_1

VCL =

voltage

range 1

Coremark

Cache on

236

—

μA/

CPU0 = Deep Sleep

Graphics and ESWM power

domain off

CPUCLK0 = 800MHz, MRICLK

= 200 MHz, MRPCLK = 12.5

MHz, ICLK = 200 MHz, PCLKA

= 12.5 MHz, PCLKB = 12.5

MHz, PCLKC = 12.5 MHz,

PCLKD = 12.5 MHz, PCLKE =

12.5 MHz, BCLK = 12.5 MHz

Cache off, executing

from ITCM

218

—

Cache off, executing

from SRAM

215

—

Cache off, executing

from MRAM

299

—

Normal

mode

All peripheral disabled,

Cache on, while (1)

code

222

—

All peripheral disabled,

Cache off, while (1)

code executing from

MRAM

297

—

CPUCLK1 =

150 MHz

VSCR_2

VCL =

voltage

range 2

Coremark

Cache on

265

—

μA/

CPU0 = Deep Sleep

Graphics and ESWM power

domain off

CPUCLK0 = 600MHz, MRICLK

= 150 MHz, MRPCLK = 9.4

MHz, ICLK = 150 MHz, PCLKA

= 9.4 MHz, PCLKB = 9.4 MHz,

PCLKC = 9.4 MHz, PCLKD =

9.4 MHz, PCLKE = 9.4 MHz,

BCLK = 9.4 MHz

Cache off, executing

from ITCM

247

—

Cache off, executing

from SRAM

244

—

Cache off, executing

from MRAM

326

—

Normal

mode

All peripheral disabled,

Cache on, while (1)

code

252

—

All peripheral disabled,

Cache off, while (1)

code executing from

MRAM

324

—

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

RA8D2 Datasheet

2. Electrical Characteristics

R01DS0493EJ0130 Rev.1.30

Feb 27, 2026

Page 78 of 292

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