R7KA8D2AFDCAC datasheet(61/292 Pages) RENESAS

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Table 2.10

Current of high-speed mode, maximum condition (MVE and peripheral operation), CPU0 active, CPU1

Deep Sleep (DCDC mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

Supply

current

*1*2*5

—

ICC

3.85

6.27

6.69

—

CPUCL

K0 = 1

GHz

CPUCL

K1 =

250

MHz

VSCR_

VCC_DCDC

≥ 2.5 V

ICC_DCDC *4

174

346

—

VCC_DCDC = 3.3 V

MRICLK = 250MHz, MRPCLK = 125 MHz,

ICLK = 250 MHz, BCLK = 125 MHz, PCLKA

= 125MHz, PCLKB = 62.5 MHz, PCLKC = 125

MHz, PCLKD = 250 MHz, PCLKE = 250 MHz

CPU1 = Deep Sleep

IDD *3

447

889

—

VCC_DCDC

< 2.5 V

ICC_DCDC *4

340

676

—

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

447

889

—

CPUCL

K0 =

800

MHz

CPUCL

K1 =

200

MHz

VSCR_

VCC_DCDC

≥ 2.5 V

ICC_DCDC *4

147

—

363

VCC_DCDC = 3.3 V

MRICLK = 200 MHz, MRPCLK = 100 MHz,

ICLK = 200 MHz, BCLK = 100 MHz, PCLKA

= 100 MHz, PCLKB = 50 MHz, PCLKC = 100

MHz, PCLKD = 200 MHz, PCLKE = 200 MHz

CPU1 = Deep Sleep

IDD *3

376

—

933

VCC_DCDC

< 2.5 V

ICC_DCDC *4

286

—

710

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

376

—

933

CPUCL

K0 =

600

MHz

CPUCL

K1 =

150

MHz

VSCR_

VCC_DCDC

≥ 2.5 V

ICC_DCDC *4

115

309

314

VCC_DCDC = 3.3 V

MRICLK = 150 MHz, MRPCLK = 75 MHz, ICLK

= 150 MHz, BCLK = 75 MHz, PCLKA = 75 MHz,

PCLKB = 37.5 MHz, PCLKC = 75 MHz, PCLKD

= 150 MHz, PCLKE = 150 MHz

CPU1 = Deep Sleep

IDD *3

300

750

823

VCC_DCDC

< 2.5 V

ICC_DCDC *4

224

559

614

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

300

750

823

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Measured with clocks supplied to the peripheral functions and peripherals being operated. This does not include the BGO

operation.

Note 3. IDD depends on f (CPUCLK0 and ICLK) as follows.

IDD Typ. = 0.25 × fCPUCLK0 + 0.74 × fICLK + 21 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 95℃) = 0.22 × fCPUCLK0 + 0.96 × fICLK + 487 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 105℃) = 0.22 × fCPUCLK0 + 0.96 × fICLK + 565 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 95℃) = 0.22 × fCPUCLK0 + 0.97 × fICLK + 474 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 105℃) = 0.22 × fCPUCLK0 + 0.97 × fICLK + 549 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 4. Typical DCDC efficiency and the voltage of the test conditions are applied.

Note 5. The power consumption is calculated as Power = VCC × Icc + VCC_DCDC × Icc_DCDC.

RA8D2 Datasheet

2. Electrical Characteristics

R01DS0493EJ0130 Rev.1.30

Feb 27, 2026

Page 61 of 292

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