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R7KA8D2AFDCAC bảng dữ liệu(HTML) 68 Page - Renesas Technology Corp |
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68 / 292 page ![]() Table 2.22 Current of high-speed mode, maximum data processing, CPU0 Deep Sleep, CPU1 active, peripheral clock OFF (DCDC mode) Parameter Symbol Typ Max Unit Test conditions 95 °C 105 °C Supply current *1*2 CPUCLK0 = 1 GHz CPUCLK1 = 250 MHz VSCR_1 ICC_DCDC*4 29 161 — mA VCC_DCDC = 3.3 V CPU0 = Deep Sleep *3 IDD 73 413 — CPUCLK0 = 800 MHz CPUCLK1 = 200 MHz VSCR_1 ICC_DCDC*4 25 — 182 IDD 65 — 467 CPUCLK0 = 600 MHz CPUCLK1 = 150 MHz VSCR_2 ICC_DCDC*4 21 145 171 IDD 54 381 448 Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state. Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation. Note 3. Same frequency condition is applied as in the maximum condition. Note 4. Typical DCDC efficiency and the voltage of the test conditions are applied. Table 2.23 Current of high-speed mode, maximum data processing, CPU0 Deep Sleep, CPU1 active, peripheral clock OFF (External VDD mode) Parameter Symbol Typ Max Unit Test conditions 95 °C 105 °C Supply current *1*2 CPUCLK0 = 1 GHz CPUCLK1 = 250 MHz VCL = voltage range 1 IDD 73 413 — mA CPU0 = Deep Sleep *3 CPUCLK0 = 800 MHz CPUCLK1 = 200 MHz VCL = voltage range 1 IDD 65 — 467 CPUCLK0 = 600 MHz CPUCLK1 = 150 MHz VCL = voltage range 2 IDD 54 381 448 Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state. Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation. Note 3. Same frequency condition is applied as in the maximum condition. RA8D2 Datasheet 2. Electrical Characteristics R01DS0493EJ0130 Rev.1.30 Feb 27, 2026 Page 68 of 292 |
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