R7KA8D2AFDCAC datasheet(59/292 Pages) RENESAS

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Table 2.8

Current of high-speed mode, maximum condition (MVE and peripheral operation) (DCDC

mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

Supply

current

*1 *2*5

—

ICC

3.85

6.27

6.69

—

CPUCL

K0 = 1

GHz

CPUCL

K1 =

250

MHz

VSCR_

VCC_DCDC

≥ 2.5V

ICC_DCDC *4

183

358

—

VCC_DCDC = 3.3 V

MRICLK = 250 MHz, MRPCLK = 125 MHz,

ICLK = 250 MHz, BCLK = 125 MHz, PCLKA =

125 MHz, PCLKB = 62.5 MHz, PCLKC = 125

MHz, PCLKD = 250 MHz, PCLKE = 250 MHz

IDD *3

469

918

—

VCC_DCDC

< 2.5V

ICC_DCDC *4

357

698

—

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

469

918

—

CPUCL

K0 =

800

MHz

CPUCL

K1 =

200

MHz

VSCR_

VCC_DCDC

≥ 2.5V

ICC_DCDC *4

153

—

373

VCC_DCDC = 3.3 V

MRICLK = 200 MHz, MRPCLK = 100 MHz,

ICLK = 200 MHz, BCLK = 100 MHz, PCLKA

= 100 MHz, PCLKB = 50 MHz, PCLKC = 100

MHz, PCLKD = 200 MHz, PCLKE = 200 MHz

IDD *3

394

—

957

VCC_DCDC

< 2.5V

ICC_DCDC *4

299

—

728

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

394

—

957

CPUCL

K0 =

600

MHz

CPUCL

K1 =

150

MHz

VSCR_

VCC_DCDC

≥ 2.5V

ICC_DCDC *4

119

294

323

VCC_DCDC = 3.3 V

MRICLK = 150 MHz, MRPCLK = 75 MHz, ICLK

= 150 MHz, BCLK = 75 MHz, PCLKA = 75 MHz,

PCLKB = 37.5 MHz, PCLKC = 75 MHz, PCLKD

= 150 MHz, PCLKE = 150 MHz

IDD *3

312

769

845

VCC_DCDC

< 2.5V

ICC_DCDC *4

233

574

630

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

312

769

845

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Measured with clocks supplied to the peripheral functions and peripherals being operated. This does not include the BGO

operation.

Note 3. IDD depends on f (CPUCLK0 and ICLK) as follows. The ICLK items in the formula include CPU1 current.

IDD Typ. = 0.25 × fCPUCLK0 + 0.87 × fICLK + 21 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 95℃) = 0.22 × fCPUCLK0 + 1.07 × fICLK + 490 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 105℃) = 0.22 × fCPUCLK0 + 1.07 × fICLK + 549 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 95℃) = 0.22 × fCPUCLK0 + 1.09 × fICLK + 477 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 105℃) = 0.22 × fCPUCLK0 + 1.09 × fICLK + 552 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 4. Typical DCDC efficiency and the voltage of the test conditions are applied.

Note 5. The power consumption is calculated as Power = VCC × Icc + VCC_DCDC × Icc_DCDC.

RA8D2 Datasheet

2. Electrical Characteristics

R01DS0493EJ0130 Rev.1.30

Feb 27, 2026

Page 59 of 292

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