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TMP411 bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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TMP411 bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 48 page ![]() 7 TMP411 www.ti.com SBOS383D – DECEMBER 2006 – REVISED DECEMBER 2016 Product Folder Links: TMP411 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated (1) For cases with an SCL fall time of less than 20 ns, or an SDA rise or fall time of less than 20 ns, the hold time must be greater than 20 ns. (2) For cases with an SCL fall time of less than 10 ns, or an SDA rise or fall time of less than 10 ns, the hold time must be greater than 10 ns. 7.6 Timing Requirements MIN NOM MAX UNIT f(SCL) SCL operating frequency Fast mode 0.001 0.4 MHz High-speed mode 0.001 3.4 t (BUF) Bus free time between STOP and START condition Fast mode 600 ns High-speed mode 160 t (HDSTA) Hold time after repeated START condition. After this period, the first clock is generated Fast mode 100 ns High-speed mode 100 t (SUSTA) Repeated START condition setup time Fast mode 100 ns High-speed mode 100 t (SUSTO) STOP condition setup time Fast mode 100 ns High-speed mode 100 t (HDDAT) Data hold time Fast mode 0 (1) ns High-speed mode 0 (2) t (SUDAT) Data setup time Fast mode 100 ns High-speed mode 10 t (LOW) SCL clock LOW period Fast mode 1300 ns High-speed mode 160 t (HIGH) SCL clock HIGH period Fast mode 600 ns High-speed mode 60 t F Clock and data fall time Fast mode 300 ns High-speed mode 160 t R Clock and data rise time Fast mode 300 ns High-speed mode 160 SCLK ≤ 100 kHz Fast mode 1000 High-speed mode |
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